Hardware filtering of input packet identifiers for an MPEG re-multiplexer

ABSTRACT

An input filter for use in a re-multiplexing module to process input packet data, includes an input interface that receives the input packet data, an input processor that is designed to write data to a packet buffer, and a packet identifier table containing PID values for filtering the input packet data. The input filter is implemented as hardware, thereby eliminating the limitations encounted in software filtering of data packets.

TECHNICAL FIELD

[0001] The present invention relates to the field of signalmultiplexing, and more particularly to a packet processing system foruse in a digital cable television headend for re-multiplexing high-speedvideo, audio, and data signals.

BACKGROUND OF THE INVENTION

[0002] Re-multiplexers are often used in cable television systems forefficient data transmission from a content source to a consumer. Thecontent source usually provides the cable operator with programs via oneor more input transport streams, often in the form of MPEG transportstreams. The simplest way to transmit the programs to the consumer wouldbe for the cable operator to simply transmit all of the input transportstreams it receives to a terminal at the consumer's location. However,this method would unnecessarily waste output bandwidth because not everyconsumer would be given access to every program in the transport stream.

[0003] Currently known MPEG re-multiplexers can obtain programs frommultiple input transport streams and re-multiplex them into a singleoutput stream containing selected programs, thereby preserving outputbandwidth. However, there are some applications where it is desirable togenerate two or more output streams from the input streams. There ispresently no known re-multiplexer that can construct more than oneoutput stream from multiple input streams.

[0004] Further, re-multiplexers often use filtering software to comparethe input packets with packet identifier (PID) values and determinewhich packets in the input are suitable for re-multiplexing and outputas well as to detect and discard defective packets. Using software tofilter input packets tends to limit the number of PID values that can beused by the re-multiplexer. If the re-multiplexer is used as a module ina packet processing system, software operations focusing on packetfiltering may divert limited software resources from other modules.

[0005] There is a need for a system that filters input packets enteringa re-multiplexer without the limitations encountered by known software.

SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention is directed to an input filterfor use in a re-multiplexing module to process input packet data, thedevice including an input interface that receives the input packet data,an input processor that is designed to write data to a packet buffer,and a packet identifier table containing PID values for filtering theinput packet data.

[0007] By placing the filtering operations in the hardware of there-multiplexing module rather than relying on software to conduct thefiltering, the inventive hardware filter is not constrained by anylimitations on the number of input stream PIDs that can bere-multiplexed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram of a re-multiplexer module according tothe present invention;

[0009]FIG. 2 is a block diagram of an input processor in the module ofFIG. 1;

[0010]FIG. 3 is a block diagram of a packet identifier table in themodule of FIG. 1;

[0011]FIG. 4 is a block diagram of an output processor in the module ofFIG. 1; and

[0012]FIG. 5 is a flowchart illustrating an interrupt service routineused by the module of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]FIG. 1 is a block diagram illustrating one embodiment of there-multiplexing module 100 according to the present invention. Theremultiplexing module 100 can be used as one component in a packetprocessing system in conjunction with other functional modules, such asan system controller or integrated backplane to create a reconfigurableprocessing element supporting high-speed transport of video, audio anddata signals for digital cable television headends. In the descriptionbelow, it is assumed that the signals are in an MPEG-2 format, but it isto be understood that the inventive system can be used to processsignals in other compatible formats without departing from the scope ofthe invention. Further, although the example below receives six MPEG-2input transport streams and generates two independent MPEG-2 outputtransport streams, the inventive system can support and generate anynumber of inputs and/or outputs.

[0014] In general, the inventive re-multiplexing module 100 acceptsmultiple input transport streams and generates new, independent outputtransport streams containing selected programs from the input streams.In addition to the re-multiplexing function, the inventive system alsoallows message extraction from all of the input streams and messageinsertion into all of the output streams.

[0015] As shown in FIG. 1, the inventive system 100 includes an inputprocessing (“IP”) section 102, one or more packet buffers 104, an outputprocessing (“OP”) section 106, a clock generator 108, message extractionsection 110, packet inserter 112, a host controller 114, and systeminterface 116. Each of these portions will be described in greaterdetail below.

[0016] The input processing section 102 includes a backplane inputinterface circuit 118, an input processor 120, and a packet identifier(PID) filter table 122 for each input data stream. The input processor120 can be implemented as, for example, a field programmable gate arrayor a programmable logic device. In this example, there are six inputinterfaces 118, PID filter tables 122, and input processors 120, so thisembodiment can accept six separate MPEG-2 input streams. The six inputstreams can be asynchronous and can have different information rates.The input processing section 102 is designed to accept the inputstreams, drop undesired packets, and store the accepted packet data, aninput timestamp, and control information in the packet buffers, wherethey are presented to the output processor.

[0017] The input packet data sent to the input interface circuits 118 inthe input processing section 120 can be clocked and re-clocked usingdiscrete, high-speed logic and sent to a corresponding input processor120.

[0018]FIG. 2 is a representative diagram illustrating the components ofthe input processor 120 for one channel, which receives the input datafrom one input interface circuit 118. Functionally, the input processor120 performs all of the required front-end packet data processing beforethe data is stored in the packet buffers 104 thereby eliminating theneed for software to carry-out these operations. Generally, the inputprocessor 120 functions may include serial-to-parallel conversion of theinputs from the input interface circuits 118, filtering and dropping anypackets that are not selected to be output in one of the output streamsor to be extracted, and checks for and discards invalid MPEG packets inthe input stream. The input processor 120 also may identify and flagpackets having valid program clock reference (PCR) data to reduce theprocessing load on the output processor; this is conducted by checkingwhether an adaptation field exists in an MPEG packet input to the inputprocessor and, if one exists, checking the status of a PCR flag bit inthe adaptation field. The input processor 120 may also generate inputtimestamps used for PCR correction, write desired packets into thepacket buffer for output processing, write timestamps and other packetinformation required by the output processor into the packet buffer, andact as a control/status interface to the CPU.

[0019] Referring to FIG. 2 in more detail, input data is sent to aserial-to-parallel converter 200, which converts the serial input streamfrom the input interface 118 to 8-bit parallel data. This conversionsimplifies the input processor 120 timing and control. Each inputinterface 118 contains four signals: PDATA, PSYNC, PCLK, and RCLK, wherePCLK is synchronous with PDATA and PSYNC. A byte clock is derived fromthe PCLK signal in the input interface 118 by dividing PCLK by eight.The byte clock drives the datapath logic.

[0020] The converted data from the serial-to-parallel converter 200 isthen sent to an input processor (IP) control logic block 202, whichgenerates all of the required control and timing signals for the otherprocessing elements in the input processor 120. One function of the IPcontrol logic 202 is to validate input packets in the input data stream.More particularly, the IP control logic 202 extracts the PID number fromthe MPEG of the input packets in the 8-bit parallel data and sends thePID number to the address lines of the PID table 122 as well as a PIDnumber buffer 203. If the PID table 122 returns a “valid” bit, eitheralone or with a “priority” bit if the IP control logic 202 is in apriority mode, the packet will be considered validated and send to thepacket buffer 104 for storage. The details of the valid and prioritybits will be described in greater detail below with respect to PIDfiltering.

[0021] The input control logic 202 also checks the incoming packet datafor proper MPEG packet length. More particularly, when a sync signal isdetected (i.e., when PSYNC=1) coincident with a data byte of 0×47, abyte counter (not shown) in the input control logic 202 is initializedand then increments with each clock of PCLK. If the next sync eventoccurs before the byte counter reaches a predetermined number of bytes(e.g., 188 bytes), then the IP control logic 202 considers the packetlength invalid, discards the packet, and asserts an error bit that isreadable by the host processor 114. If, however, the sync event isdetected immediately after the byte counter reaches the predeterminedvalue, the input control logic considers the packet the correct size andis therefore available for re-multiplexing. Note that this packet lengthtest can also be incorporated into “input active” circuitry at the inputinterfaces 118 for detecting valid data at each input. In this case, an“input active” status bit is available to the processor 114 and can alsobe monitored via a LED on the re-multiplexer module 100.

[0022] Note that because the input processor 120 writes data to thepacket buffer 104 as the data is received, the IP control logic 202 willnot detect if the packet length is correct until the end of the packet.As a result, a page counter in the packet buffer 104 will not beincremented if the packet length is incorrect, and the pagecorresponding to the defective packet will by overwritten in the bufferby the next valid input packet received. Also, input packets containingan asserted transport error bit can be discarded via an optional modecontrolled by the host processor 114. The transport error bit can beasserted by equipment, such as an encoder, that processes the MPEGstream and that can detect an error in the MPEG packet before it reachesthe re-multiplexer module. If the transport error bit in the IP controllogic block 202 is set and a transport error is detected, writing to thepacket buffer 104 will be disabled (e.g., by not asserting a writeenable signal), and the packet having the transport error bit will notbe written into the packet buffer 104.

[0023]FIG. 2 also shows a time reference generator 204 in the inputprocessor, which generates a time stamp for each valid input packet andstores it in a time stamp sample register 206. The time stamp is used byPCR correction circuitry in the output processor, to calculate the timethat the input packet takes to pass through the re-multiplexer module.To calculate the time stamp in this example, a snapshot is taken of a20-bit time reference running at 27 MHz when the last byte of a packethas been received by the input processor 120. This time stamp isgenerated at the end of each packet to avoid putting any minimum datarate restrictions on the inputs.

[0024] Next, PCR detection block 208 in the input processor 120 monitorsinput packets for a valid PCR field and writes a PCR flag to the packetbuffer 104. Because PCR timestamp reads will only be necessary frompackets containing valid PCR fields, the output processing portion 106uses the PCR flag information to minimize the number of read operationsthat it must perform from the output processor by highlighting thelocation of the valid PCR fields via the PCR flags. To detect thelocation of valid PCR fields, the PCR detector 208 first checks the PCRflag bit in an adaptation field in the packet (in this example, thisfield is at byte 4, bit 5) for a 1 bit. The PCR detector 208 then checkstwo scramble control bits in the packet for a 00, indicating that thedata is not scrambled. If the scramble control bits indicate that thepacket is scrambled, the PCR bit is invalid and the packet is discarded.If the data is not scrambled and the PCR flag=1, then the packet will bemarked as a PCR packet by setting a selected bit in a packet bufferlocation assigned for PCR packet identification purposes.

[0025] The input packet data and address data is directed to the packetbuffers via a data multiplexer 210 and address multiplexer 212 under thecontrol of timing and control circuitry. As can be seen in FIG. 2, thedata multiplexer 210 receives PID number data, the PCR detector output,page number data, and the input timestamp, while the address multiplexer212 receives location information. Because the packet buffer mustaccommodate the input timestamp, PCR flag, the PID number and the pagenumber for each packet as well as the packet itself, the write controllogic provided by the IP control logic block 202 preferably operates attwice the packet word rate so that it can service more than one outputand to ensure that the additional control information, such as thetimestamp and the PCR flag, is read for each packet in its entirety. Thewrite control logic also interleaves the control data with MPEG packetdata. One possible storage scheme involves storing the timestamp withits associated packet, after the 94-word packet block, and storing thePCR flag, page number, and PID number in the last two locations of thepacket buffer 104. In this example, when the last word of the packetbuffer 104 (in this example, location 8191) is written, the dual portRAM (DPRAM) used for each packet buffer generates an interrupt signaland sends it to the output processor.

[0026] A data delay register 214 also sends a signal to the datamultiplexer 210 to control the flow of packet data to the packet buffer104. In one embodiment, the data delay register 214 causes the inputprocessor 210 to delay the packet data by four clock cycles to performerror check and validate packets before any data can be written to thepacket buffer. The data delay allows error checking and validation tooccur without any data loss. If, after error checking and validation,the packet is allowed to be written to the packet buffer via the delayeddata path created by the data delay register.

[0027] A page number generator 216 may also provide a signal to the datamultiplexer 210 corresponding to a page number for packets stored in thepacket buffer 104. More particularly, the page number generator 216maintains a byte counter for each input packet. When a sync is detected,an 8-bit byte counter in the page number generator is loaded with a zerovalue and then is counted upward as each new byte is received. In oneembodiment, the lower 7 address bits in the packet buffer contains adelayed version (e.g., delayed by 4 clocks) of the 8-bit byte counterwithout the least significant bit. The least significant bit is not usedin the packet buffer 104 because the input processor writes 16-bit wordsin the packet buffer 104 at one time; because the packet buffer storestwo bytes in the same location, every other count of the 8-bit bytecounter is not required for reporting. Once a validated packet has beenstored in the packet buffer 104, the page number generator 216increments the page number. The page number itself is the upper 6 bitsof the packet buffer 104. The lower 7 address bits and the upper 6 bitstogether form the 13 bits of address space in the packet buffer.

[0028] As can also be seen in FIG. 2, the input processor 120 has a hostprocessor interface 218 that acts as a control and status registerinterface to the re-multiplexer module host processor 114. There-multiplexer host processor 114 controls the packet data flowoperation and reads the input processor 120 status as packets travelthrough the re-multiplexer module 100.

[0029] As mentioned above, the input processing portion 102 alsoincludes a PID filter table 122 associated with each input stream. Anexample of a PID filter table 122 used in the inventive re-multiplexeris shown in FIG. 3. The PID filter table 122 stores values against whichinput packets are evaluated and stored or dropped. In one embodiment,the PID filter tables 122 are stored in multi-port accessible memories,such as a dual-port RAM. As can be seen in FIG. 3, the PID filter table122 can be partitioned into two separate tables, a lower table 300 andan upper table 302, to allow dynamic reconfiguration. The lower andupper tables 300, 302 act interchangeably as an active PID table or apending PID table. In this example, the lower table 300 acts as theactive PID and the upper table 302 acts as the pending PID table. Eachof the individual possible PID values (in this example, 8192 possiblevalues) maps to a single particular location in the active PID table,and each location in the active PID table contains a valid bit 304, apriority bit 306 and 6 reserved bits 308.

[0030] PID values from MPEG packets in the input stream are sent to theaddress lines of the PID filter table 122. The PID filter table outputsdata corresponding to each address contains re-multiplexing informationfor the specific PID at that address. If the valid bit 304 for the PIDvalue in a given packet is cleared, that packet is dropped and notwritten to the packet buffer 104. If, however, the valid bit 304 isasserted, the packet is stored in the packet buffer 104 to awaitre-multiplexing. The priority bit 306 in the packet provides anadditional level of packet filtering by distinguishing between validpackets. Priority mode occurs when the packet data is reaching a maximumrate, and the command to activate priority filtering can be received bythe input processor 120 from software. In priority mode, a packet havingthe priority bit 306 asserted indicates that the packet has a higherpriority than other valid packets and should therefore be passed throughthe re-multiplexer 100 before valid packets without an asserted prioritybit.

[0031] The status of the tables 300, 302 can be switched between activeand pending status via software control by the host processor 114, ofthe most significant bit of the PID table 122 which acts as a controlbit. While the input processor 120 is operating from the active table,the host processor 114 on the re-multiplexer module 100 can modify thepending table, thereby allowing modifications in the PID table withoutinterrupting input processor operation. When the host processor 114chooses to put the pending table into effect, it modifies the mostsignificant bit in the PID table 122, which acts as a control bit. Theinput processor 114 then registers the control bit with the PCLKassociated with that data stream so that, on the next sync event forthat data stream, the PCLK switches the statuses of the two tables 300,302, turning the pending table into the current active table and turningthe active table into the current pending table. The control bit becomesthe most significant bit of the input processors interface to the PIDtable, and the host processor can read this bit directly from an inputprocessor status register. Once the host processor modifies the mostsignificant bit in the PID filter table, it should not attempt to writenew table data until it validates that the status has indeed beenswitched.

[0032] The packet buffers 104 provide the interface from the sixindependent input processors 120 to a single synchronous interface of anoutput processor 124 in the output processing portion 106. The packetbuffer 112 can be divided into types: an input packet buffer and aninsert packet buffer. The input packet buffer can be the packet buffers104 shown in FIG. 1 for holding data from all accepted packets. Eachinput stream preferably has a dedicated input packet buffer, such as an8K×16 DPRAM, each of which acts as a circular buffer. In one embodiment,the accepted packet data is stored in blocks of 256 bytes, allowing 64packets to be stored at one time. The minimum input buffer sizepreferably accommodates any anticipated packet jitter in there-multiplexer and may include an additional safety margin toaccommodate program streams having data bursts.

[0033] Input timestamp data, used for PCR correction, can also be storedin the input packet buffer 104 after the last data word of each inputpacket. A portion of the input packet buffer, such as the last twolocations in the buffer, can be used for storing information that willbe provided to the output processor 124. More particularly, once a newpacket has been validated and stored in the input packet buffer 104, theinput processor 120 writes the PCR flag, current page number, and PIDnumber for that packet into the last two locations of the input packetbuffer 104. The PCR flag minimizes the number of status reads conductedby the output processor software because the software will read thetimestamp information for a given packet only if the PCR flag for thatpacket is set. The page number notifies the output processor of the newpacket's location, and the PID number of the packet is used by theoutput software in the host processor for re-multiplexing and messageextraction.

[0034] Generally, the output software in the host processor 114 allowsthe host processor to make re-multiplexing and extraction decisionsbased on the PID number identifying the MPEG stream and to pass controlinformation to corresponding hardware to perform any desired operations.When the PID number is written to the selected location in the inputpacket buffer 104, the input packet buffer portion may automaticallygenerate an interrupt that indicates to the output processor that a newpacket has been stored in the input packet buffer. The interrupt clearswhen the output processor 124 reads from the PID location in the inputpacket buffer 104. To prevent valid input data from being lost, theinput packet buffer 104 requires the output processor to read the pagenumber and PIED number information corresponding to the new packetbefore it is overwritten with the information corresponding to the nextpacket stored in the input packet buffer 104.

[0035] The other packet buffer type is an insert packet buffer 112,which can be, for example, an 8K×16 DPRAM divided into two 4K blocks,one for each output (assuming that there will be two output streams). Inone embodiment, an input port of the packet buffer 112 is coupled to thehost processor 114, and the output port is coupled to a packet bufferbus of the output processor 124. Packets designated as “insert packets”are read the same way as other packet data when selected by the outputprocessor 124, but they are inserted into the output stream to customizethe output.

[0036]FIG. 4 is a block diagram illustrating the components of theoutput processor 124 in the inventive re-multiplexing module 100. Ingeneral, the output processor 124 is a FPGA conducts the requiredhardware tasks to generate two or more output streams from the datastored in the packet buffers 104. More particularly, the outputprocessor 124 reads the selected packet data from the input packetbuffers and/or the insert packet buffer 112, performs PID remapping,program clock reference (PCR) correction and any other desired orrequired packet editing, and may also insert new PID fields and otherMPEG control information into the output streams as directed by the CPU.The output processing section then generates two or more independenthigh-speed transport multiplex (HSTM) output streams incorporating theselected packet data. The output processing section also monitors thepacket buffers 104, 112 to check for any newly arrived packets and tocommunicate to the host processor 114 of the presence of any new packetsas well as any required packet identifying information. The outputprocessing section also sends the packet data as a filtered packetstream to the message extraction portion 110. Each of the components inthe output processor 124 will be described below with reference to FIG.4.

[0037] The output processor 124 includes a bus control logic block 400that controls much of the output processor's operation. The bus controllogic 400 responds to packet buffer interrupts, reads new packetinformation from the interrupting packet buffers, and generatesaddresses and chip selects to access data in the packet buffer asinstructed by the output stream data registers. The chip selects inparticular are used by the output processor 124 to read selectedindividual “chips” in the packet buffers 104. The bus control logic 400also provides the status of the re-multiplexed outputs and a CMP outputfrom the message extraction portion 110 to the host processor 114,controls the data flow from the packet buffers 104, 112 of there-multiplexed outputs, generates the interrupt used by the hostprocessor 114 for its interrupt service routine and controls the phasesof the time domain multiplexed packet bus. The interrupt service routineis conducted by the host processor 114 in response to an interruptsignal from the bus control logic, which is triggered at regularintervals, and involves performance of re-multiplexing and extractionoperations before directing processing operation back to the start ofthe re-multiplexer code.

[0038] The bus control logic block 400 operation is conducted asfollows. The bus control logic 400 first responds to packet bufferinterrupts by monitoring an interrupt line from each of the input packetbuffers 104. Whenever an interrupt is detected from any of the inputpacket buffers 104, the new packet information for that packet in thebuffer is read and inserted into a circular buffer, which is designatedas a new packet queue 402, in a host processor interface 404. The newpacket queue preferably has a two page capacity. The bus control logicclears the interrupt by reading a second word at a designated interruptlocation in the input packet buffer 104. Note that if more than oneinterrupt occurs at one time, the interrupts will be serviced by the buscontrol logic 400 from the lowest numbered input to the highest. Thehost processor's interrupt service routine (ISR) signal is generated bya counter in the output processor 124 that creates a signal having aperiod that is slightly larger than the period of a packet received bythe re-multiplexer at a maximum input and output rate. For example, ifthe maximum input and output rate of the re-multiplexer is 52 Mbps, theISR signal generated by the host processor 114 has a period that is thesame as the period of a packet received at 53 Mbps. This differenceensures that the ISR will service all of the hardware's input and outputrequirements by finishing its processing between interrupts.

[0039] The bus control logic 400 generally controls the manner in whichthe packets are read from the input and insert packet buffers 104, 112.The reading process is generally conducted in three phase. The hostprocessor's ISR signal is divided into 94 read slots, and each read slotis divided into three time domain multiplexed phases. Each phasecontains one read cycle form the packet buffer 104. The first phaseincludes the reading of data other than the packet data itself (e.g.,timestamps, PID value, page number, PCR flag, CMP packet data). Thesecond and third phases are used to read data stored in the packetbuffers. These phases will be described in greater detail below.

[0040] The order in which the data is read during the first phase isdictated by the specific data needed to read the packet and the data'srelative priority. In this example, timestamps have the highest priorityare read first. New packet header information is considered lowerpriority and CMP packet data is considered the lowest priority. Thetimestamps are assigned the highest priority in the first phase toensure that the PCR correction calculation will be completed by the timethe resultant data is to be inserted into the output packet data stream.As explained above, packets having a valid PCR filed are detected andflagged by the input processor 120. Because the input processor 120 willreport whether or not a given packet has a valid PCR, the bus controllogic in the output processor only has to read the timestamps forpackets identified as PCR packets, skipping over packets containinginformation other than a PCR. As a result, the first phase requiresfewer timestamp reads than known processors, thereby increasing thespeed of the CMP data output because it shares the same bus controllerread phase. A prompt and quick CMP data output is desirable becausedelays in the CMP data output could cause a backup in the input packetbuffer due to an unread packet, which can cause a buffer overflow error.

[0041] If there are no timestamp reads during the first phase, the buscontrol logic will service any active packet buffer interrupts. Notethat servicing of new packet interrupts is also given a high prioritybecause the PID, page information, and PCR flag for a given packet willbe overwritten if the delay between the time the packet is stored in theinput packet buffer and the time that the packet PID and location isread completely out of the packet buffers new packet informationaddresses exceeds the period of the input packet.

[0042] If no other data is required, a pending data word can be outputto the command message processor (CMP). As noted above, prompt output ofCMP data prevents overflow errors in the input packet buffer due tobackups in the buffer caused by unread packets. Any time saved by notreading data from the packet buffer for overhead requirements makes moretime available for reading out packets to be sent to the CMP, therebyreducing or eliminating delays for CMP data outputs.

[0043] The second and third phases are used to read packet data storedin the input packet buffers and to write the data to packet datafirst-in-first-out (FIFO) buffers in the output processor 124. Thesecond phase is used to generate a first output stream and the secondphase is used to generate a second output stream, assuming that theoutput processor generates two output streams. If the re-multiplexer isdesigned to generate more than two output streams, the bus control logic400 causes the buffered data to be read in additional phases so thateach phase corresponds to one output stream. Because the packet bufferread operations in this example read one word at a time, it will takeabout 94 reads to transfer an entire packet from the input packet bufferinto the output transport stream. In this example, the data read out ofthe input packet buffers is based on the output stream data register 406in the host processor interface 404.

[0044] The host processor interface 404, which has been referencedbriefly above, is used for communication between the output processor(and specifically the bus control logic block 400 in the outputprocessor 124) and the re-multiplexer CPU. More particularly, the CPUinterface controls control and status registers as well as interfacelogic. The output processor's host processor interface 404 shown in FIG.4 contains the new packet queue status register 202, an output streamdata register 406, and an output packet status register 408. The newpacket queue status register 402 provides the re-multiplexer CPU withinformation related to any packets that have been received by the inputprocessor in between interrupt service routine events. The first word inthe new packet queue status register may include a “new packet count”field, which the host processor 114 uses to determine the number of readoperations that will be needed to transfer all of the new packetinformation.

[0045] As can be seen in the Figure, host processor data is also writtento output stream data registers in the host processor interface 404 tocontrol the content of the output streams and the CMP's source data.More specifically, the output processor 124 uses the information fromthe output stream data registers to read the data from the input packetbuffers 104, perform PCR correction, replace the existing PID with thenew output PID number corresponding to the new output packet, and setthe transport error flag. Although there are three registers in theoutput packet status register, the CPU sees the three registers as asingle write location.

[0046] The host processor interface 404 also includes output packetstatus registers 408, which output information to the host processor 114relating to the status of the two or more re-multiplexed output streamsand the CMP path, which travels from the packet buffers, through theoutput processor, to the control processor. Loading of the output streamdata register is controlled by the host processor 114 via the currentpacket information and a “done” indicator stored in the output packetstatus register.

[0047] As noted above, a packet data FIFO 410 is included in the frontend of each output stream data path. Each FIFO 140 is preferablyrelatively small (e.g., about 16 words deep) compared to the inputpacket buffers. The FIFOs 410 are included in the output processor 124because the time division multiplexing clock, which controls the phasesof the read operations from the input packet buffers, and the outputstream packet clock, which controls the data rate of the outputmultiplexing, are asynchronous. The data is read from the packet dataFIFO 410 at a fraction of the output stream packet clock rate. The FIFO410 may also include a “full” flag, such as a ¾ full flag and/or a ½full flag, which indicates to the bus control logic the fullness of theFIFO 410. The fullness of the FIFO 410 is monitored because the rate atwhich packets are sent to the output processor may be faster than therate that the packets are output into the output stream. The ½ full flagmay also be used by the output controller 414 to remove data to beinserted into the output data stream from the output processor 124.

[0048] The output processor 124 also includes a timestamp register 412associated with each output stream to store the input timestamp datafrom the input packet buffer. The timestamp information in the timestampregister will be used for PCR correction of packets having a valid PCRfield, which will be explained in greater detail below.

[0049] An output packet clock is used to determine a byte read rate andis input into the output controller 124 by the clock generator 108, asshown in FIG. 1. The output controller logic 414 controls and providesthe timing for the circuits in the output processor 124 that conductpacket data editing, PCR correction, and output stream multiplexing. Thespecific manner in which each circuit is controlled by the outputcontroller 124 will be described in greater detail below with eachindividual circuit.

[0050] First, the output controller for each data stream sends an outputto a packet data edit block 415. The packet data edit (PDE) circuitry415 is used to overwrite data in the MPEG packet. More particularly, thePDE circuit edits the PID number, transport error indicator, and legaltime window offset information. During this process, the output packet'sPID value is replaced with a new PID value that is passed to each outputprocessor output by the host processor. This PID replacement process isconducted for all of the packets sent to the output processor 124. Notethat because the final PID remapping is performed in the outputprocessor 124, after the packets have entered separate and independentdata paths, one input packet ID stream can be assigned different PIDvalues (i.e., they have unique identifiers) in each of the two outputstreams. Packets that are to be sent to the CMP will not require PIDre-mapping by the PDE circuitry because these packets will use the PIDand source value, which identifies the source from which the packet isinput, to identify the packets from the multiple input sources.

[0051] Re-multiplexing changes the temporal location of the packets,making it necessary to check a legal time window offset field withrespect to each packet. Because of this, the packet is checked for thepresence of this offset field and, if appropriate, the legal time windowvalid flag is cleared.

[0052] Software in the host processor 114 checks the fullness of theinput packet buffers for any violations of re-multiplexer packet jitterspecifications. If the input packet buffer 104 is filled to apredetermined level, the packets stored in the input buffers 104 areassumed to be corrupted. The re-multiplexing software may also check forother error conditions and can instruct the output processor to set thetransport error indicator bit in the MPEG header in all packetsassociated with any one of the outputs [why?]. Once the error conditionhas been resolved, the software will instruct the output processor 124to resume normal packet processing once the error condition has beenresolved.

[0053] A PCR correction block 416 for each output is coupled to theFIFO, time stamp register, and controller to correct for PCR jitteroccurring due to the variable amount of time in which each packet spendsin the packet buffer 104. To remove PCR jitter, the PCR correction blockfirst determines the total amount of time that a packet requires to passthrough the entire re-multiplexer module 100. The is done by calculatingthe difference between the input timestamp, which is applied when apacket first enters the packet buffer, and the output timestamp, whichis applied as the packet is removed from the packet data FIFO in theoutput processor 124. The difference between the timestamps representsthe actual delay introduced to that packet.

[0054] When the PCR value is changed, the change directly affectsdownstream decoders because any change in the difference between the PCRand the timestamp will change the amount of time that the packet willspend in the input packet buffer 104. To take advantage of this, thehost processor 114 can add a constant to the actual delay value togenerate a PCR correction value. The PCR correction value is defined asthe difference between the actual delay value and the constant value,and this PCR correction value can be positive or negative. As a result,the PCR correction value allows the re-multiplexing module 100 to adopta different multiplexing strategy than the original encoder.

[0055] A delay RAM block 418 and an output stream multiplexer block 420are also included for each output stream. The delay RAM 418 providesadditional time to allow the PCR correction block 420 to generate themodified PCR. More particularly, the delay RAM block 418 delays allpacket data from the packet data edit block 415 for a predeterminednumber of bytes, regardless of whether the packet contains a PCR field.The output stream multiplexer, which is coupled to the delay RAM and tothe PCR correction block, selects whether to obtain data from thedelayed path (through the delay RAM 418) or a PCR correction path (whichbypasses the delay RAM 418) based on the PCR bit in the output streamdata register 406. Control of the timing for the output streammultiplexer is generated by the output controller 414.

[0056] The final stage in the output processor 414 for each outputstream is a parallel-to-serial converter block 422. The convertergenerally uses the packet clock, as can be seen in FIG. 4, to convertthe parallel information from the output stream multiplexer into aserial stream. After conversion, the serial output stream is sent to anoutput interface 500 and external equipment interface 502 as shown inFIG. 1. The output interface 500 acts as the output interface to othermodules within the packet processing system, while the externalequipment interface circuitry 502 acts as the output interface toequipment outside the MPS.

[0057] As mentioned above, the output processor 414 a time referencegenerator 424. The output processor's time reference generator 420 isthe same as the time generator in the input processor except that theoutput processor time reference generator acts as the master counterthat controls synchronization between the output processor 414 and theinput processor. In one example, when the output processor's timereference generator 424 reaches a terminal count, it sends asynchronization load pulse to slave counters in the input processor 120to reload all of the counters with O's. The output timestamp is sampledwhen the first word is read from the FIFO.

[0058] A CMP output control block 426 has a byte wide interface with theoutput processor 414 and includes a clock, data, sync, data valid, and a3 bit source. Unlike the output interface 500 and the external equipmentinterface 502, which provide a constant data stream, the interface inthe CMP output control block 426 only transmits data when valid data isavailable. The 3-bit packet buffer source data is also transmitted tothe CMP output control block to distinguish between packets having thesame PID but are from different source streams.

[0059] Turning now to the message extraction portion 110 of there-multiplexer module 100, as can be seen in FIG. 1, the messageextraction portion 110 allows the re-multiplexer to perform messageextraction instead of or in conjunction with other decryption orextraction modules in the packet processing system. The messageextraction section is coupled to the output processor 124 and extractsselected messages, such as a Program Association Table (PAT), ProgramMap Table (PMT) or individual packets from the output streams. Theextracted packets or messages are stored in the extract buffer, and thecontents of the extract buffer memory can be examined by there-multiplexer's CPU or sent directly to other MPS modules (not shown)via the system interface.

[0060] Generally, a control message processor (CMP) 504 conducts theactual message extraction, while an extract message buffer 506 storesthe extracted messages. The CPU designates output packets as possiblecandidates for message extraction by setting the “valid bit” in theappropriate PID table. The output packets designated by the hostprocessor are stored in the input packet buffers along with the packetsto be re-multiplexed.

[0061] The host processor 114 notifies the output processor if a packetis to be sent to the CMP during a re-multiplexer interrupt serviceroutine. The output processor 124 reads the data from the output packetbuffer when a slot is available. The data read from the packet buffer isthen sent to the CMP 504 with a clock and an enable signal. Data will bestalled through the output processor 124 and the CMP 504 whenever a newword is not read. The rate at which the CMP 504 reads a complete packet,including timestamps, PID and source location reads results in a packetstream data rate into the CMP 504 that is approximately 90% of the datarate of the packet bus clock. The PID value of the packets sent to theCMP 504 preferably includes the packet's original PID along with a valueindicating the stream source of the packet. The stream source value canbe a 3-bit address identifying the packet buffer used by a particularinput stream, thereby allowing the CMP 504 to differentiate betweenpackets having the same PID value but were input via different inputstreams.

[0062] The CMP 504 can examine multiple PID streams simultaneously, ifneeded. The CMP itself examines incoming packet data to determine if thePID is active. If the PID is active, the message in the packet data isstored in the extract message buffer 506. When the CMP 504 detects thata complete message has been received, the CMP 504 generates an interruptsignal. At various time intervals, the host processor 114 queries theCMP 504 to determine the location and size of all messages that havebeen received by the CMP 504 since the last time the CMP 504 wasaccessed by the host processor. The host processor 114 will then notifyother modules in the MPS, via the MPS system bus in the system interface116 that a message is available in the extract message buffer 506.

[0063] The extract message buffer 506 is also connected directly to theMPS system bus (not shown) through the system interface. The systeminterface 116 writes the messages to off-board destinations directlyfrom the extract message buffer and then notifies the re-multiplexerhost processor 114 when it is finished writing messages from the extractmessage buffer, leaving the buffer available to receive new messages.The re-multiplexer host processor 114 then informs the CMP 504 of thesections available in the extract message buffer 506 are available forreceiving new messages.

[0064] The CMP 504 can also act as a packet extractor. In this example,packets are extracted based on the 4-byte MPEG header. Masking may alsobe provided in the CMP 504. If requested by the re-multiplexer hostprocessor 114, an entire packet can be stored in the extract messagebuffer, allowing the host processor 114 to check the fields in eachpayload that may be needed for re-multiplexing. The CMP 504 may alsoextract the legal time window offset field for any or all active packetsto be used in PCR correction. The host processor 114 accesses theextract message buffer 506 through the CMP 504, as can be seen in theFigure, and can read portions of any packet or any extracted message inthe extract message buffer and determine whether the information in thepacket or message is unwanted or redundant. The host processor 114 willthen notify the CMP 504 that the packet or message can be cleared onceit has been read. The interface between the CMP 504 and the extractmessage buffer 506 is preferably time-division multiplexed to allow hostprocessor 114 read operations.

[0065] The packet insertion function, which is performed by the outputprocessor 124 and insert packet buffer 112 in conjunction with the hostprocessor 114, inserts messages in any of the output streams. Themessage insertion function allows the re-multiplexer to produce MPEGcompliant output transport streams while keeping its data processingload at a manageable level. Insert messages are sent to there-multiplexer over the system bus. The source of the messages willtypically be the controlling element in the packet processing system(not shown). An insertion queue manager executing in software packetizesthe messages and schedules the packet insertion into the output streams.In the re-multiplexer interrupt service routine, the software alsochecks for the availability of a packet whenever one of the outputqueues is empty. Insert packets are read the same way as the inputpacket data when the are selected by the CPU. The insert packet buffer112 itself can be a DPRAM that is divided into multiple blocks, oneblock associated with each output. In this example, the input packetbuffer is an 8K×16 DPRAM divided into two 4K blocks, one for eachoutput.

[0066] The host processor 114 section of the re-multiplexer modulecontrols all of the remultiplexing decisions in the module. One possiblehost processor 114 may contain a 200 MHz processor 508, 1 Mbyte of mainmemory (e.g., a synchronous burst static RAM) 510, 2 Mbytes of flashmemory 512 for non-volatile program storage, a universal asynchronousreceiver/transmitter, a memory/interrupt controller 814 implemented in ahigh-speed complex programmable logic device, and associated supportlogic.

[0067] The host processor 114 section in this example acts as the hostprocessor and provides the data used to filter out unwanted packets,directs the output processing hardware in creating the re-multiplexedoutputs and CMP 504 streams, monitors the input data for overflowconditions, generates values used for PCR correction, selects the outputrates, and provides status and control interfaces to the majorprocessing elements, as described above, in the re-multiplexing module.The host processor 114 also communicates with the MPS system controller(not shown ) via the system interface 116.

[0068] The host processor 114 includes an interrupt and memorycontroller 514, which performs address decoding and generates handshakesignals that are needed to control the processor's access to otherelements of the re-multiplexer module 100. The interrupt and memorycontroller 514 can be in the form of a high-speed programmable logicdevice. The memory controller also generates the control signals neededfor storing programs in flash memory and executing programs out of thehigh-speed burst memory and can also function as an interruptcontroller.

[0069] The memory controller 514 also monitors the address bus andcontrol lines to determine which portion of the re-multiplexer module100 is being accessed by the host processor. In addition to performingaddress decoding, the controller may also recognize burst transfers andprovide the control signals to the burst RAM 510 to access program data,provide control signals to flash transceivers to allow 64-bit reads andwrites, generate wait states for the devices in the re-multiplexermodule 100, and steers data to appropriate byte lanes within theprocessor databus.

[0070]FIG. 5 is a flowchart illustrating one example of an interruptservice routine that is conducted in the re-multiplexer software. Theinterrupt service routine is initiated at step 515 by a signal generatedby the output processor and sent to the host processor 114. Once theinterrupt service routine is initiated, the hardware in the outputprocessor 124, which reads the page and PID number information from thepacket buffers and sends the information to the host processor 114, ischecked to determine the source and PID of any packets stored in theinput packet buffers since the previous interrupt service routine atstep 516. If new packets are detected at step 518 (that is the newpacket count does not equal 0), the 3-bit source address and PID areused to determine the destination (e.g., any one of the output streams,the CMP, or any combination) for the new packets at step 520. If the newpackets are re-multiplexed, the new packets are placed on the new packetqueue with information corresponding to its location in the packetbuffer, its final PID and its PCR correction constant. If the new packetis to be sent to the CMP 504, the new packet is placed on the CMP queuewith only its packet location. This example assumes that the outputprocessor has one output packet queue that is latched for the hostprocessor 514 and another output packet queue that gathers new packetinformation during the interrupt service routine.

[0071] Next, the host processor 114 collects data from any new packetsthat have entered the input packet buffers during the previous interruptservice routine period. Because, in this example, the PPC INT signaloccurs at a faster rate than the fastest possible input, no more thanone packet can be received in any of the input packet buffers during oneISR period. The collected data also allows the host processor 114 todetect input packet buffer overflow at step 524.

[0072] As noted briefly above, the fullness of each of the packetbuffers 104 should be monitored by the host processor 114. In oneexample, the software checks the packet buffers 104 for an “almost full”condition, a “half full” condition, and an “almost empty” condition.During normal operation, the input packet buffer 104 will contain fewpackets. If the input packet buffer passes the half-full point, theinput processor 120 is instructed to check the priority bit in thepackets and filter non-priority packets, as noted above with respect topriority mode operation. The priority mode is preferably maintaineduntil the packet buffer 104 returns to an almost empty state.

[0073] If the packet buffer 104 continues to become increasingly fulleven during the priority mode and passes the “almost full” threshold,the packet input is turned off completely to prevent additional packetsfrom entering the input buffers. When the re-multiplexing softwaredetermines that the input buffer is almost empty, it allows inputpackets to enter the input packet buffer again. When the input is turnedback on, the input processor resumes writing to the input packet bufferat the location it was writing when the input was turned off. Also, ifthe processing mode of an input stream changes, the system controllerfor the packet processing system (not shown) is notified. If an actualinput packet buffer overflow is detected, the input processor will beturned off by the host processor and the output processor sets thetransport error indicator in any outgoing packets.

[0074] The re-multiplexing software also monitors the number of packetsin each output queue at step 526. Any fluctuations in the number ofpackets in the output queues determines the maximum packet jitter, andfrom this information a value is selected as a maximum allowable numberof packets in each output queue. Whenever this value is exceeded by anyoutput packet queue, an output overflow flag the software is enabled andany new packets will be dropped until the output queue is empty.

[0075] Next, the hardware is checked to determine if any output streamdata register information is needed for any of the outputs or for theCMP 504. Any information is passed for the oldest entry in the outputqueue within the host processor software. If the output queue is emptyand an insert packet is available in the insert packet buffer, thelocation of that insert packet is passed into the output stream at step530. Otherwise, the location of the null packet is passed into theoutput stream.

[0076] If there is an input buffer overflow, the system disables theinput or configures a priority mode to select which packets should beprocessed first. If there is no input buffer overflow or after the inputis disabled or the priority mode is configured, the host processor 114reads the output packet status register and checks whether the readoperation is complete for each output stream and CMP. If the readoperation is not complete, the next pending packet is loaded into theoutput stream data register and the interrupt service routine ends.

[0077] A system interface 116 links the re-multiplexer module to othermodules (not shown) in the MPS system via a parallel system bus.Information that can be sent to the re-multiplexer includeinitialization and configuration parameters, processing commands, andmessages to be inserted into the output stream. Information that can besent by the re-multiplexer to other MPS modules include there-multiplexer module status, processing errors, and extracted messages.Note that, in practice, most of the communication will be between there-multiplexer module and the system controller module.

[0078] Parallel bus access is controlled by the system interface FPGA532, and data being sent to or from the re-multiplexer module is storedin a dedicated DPRAM in the re-multiplexer module 534.

[0079] It should be understood that various alternatives to theembodiments of the invention described herein may be employed inpracticing the invention. It is intended that the following claimsdefine the scope of the invention and that the method and apparatuswithin the scope of these claims and their equivalents be coveredthereby.

What is claimed is:
 1. An input processing device for use in are-multiplexing module that processes input packet data, comprising: aninput interface that receives the input packet data; an input processorcoupled to the input interface to receive input packet data therefromand write data to a packet buffer; and a packet identifier table coupledto the input processor.
 2. The input processing device of claim 1,wherein the input processor includes a serial-to-parallel converter forconverting the input packet data received from the input interface. 3.The input processing device of claim 1, wherein the input processorincludes a input processor control logic portion that validates theinput packet data.
 4. The input processing device of claim 3, whereinthe input processor control logic validates the input packet data byextracting a packet identifier number from a header in the input packetdata and checking the packet identifier number with the packetidentifier table.
 5. The input processing device of claim 1, wherein theinput processor includes a program clock reference detector that checksthe input packet data for a valid program clock reference field.
 6. Theinput processing device of claim 1, wherein the input processor includesa data delay register that delays the input packet data before the inputprocessor writes data to the packet buffer.
 7. The input processingdevice of claim 1, wherein the input processor includes a time referencegenerator that generates timestamp values for the input packet data. 8.The input processing device of claim 1, wherein the input processorincludes a host processor interface.
 9. The input processing device ofclaim 1, wherein the input processor is a field programmable gate array.10. The input processing device of claim 1, wherein the packetidentifier table is divided into an active table containing values usedby the input processor to select packets for storage in a input packetdata stream and a pending table containing values that can be modifiedby the host processor while the active table is being used by the activetable.
 11. An input processing device for use in a re-multiplexingmodule that processes input packet data, comprising: an input interfacethat receives the input packet data; an input processor coupled to theinput interface to receive input packet data therefrom and write data toa packet buffer, the input processor including a serial-to-parallelconverter for converting the input packet data received from the inputinterface; an input processor control logic portion that receives datafrom the serial-to-parallel converter; a program clock referencedetector that checks the input packet data for a valid program clockreference field; a data delay register that delays the input packet databefore the input processor writes data to the packet buffer; a timereference generator that generates timestamp values for the input packetdata; and a host processor interface; and a packet identifier tablecoupled to the input processor.
 12. The input processing device of claim11, wherein the input processor is a field programmable gate array. 13.The input processing device of claim 11, wherein the packet identifiertable is divided into an active table containing values used by theinput processor to select packets for storage in a input packet datastream and a pending table containing values that can be modified by thehost processor while the active table is being used by the active table.14. The input processing device of claim 11, wherein the input packetdata includes a plurality of packets, and wherein the input processorcontrol logic portion validates the input packet data by extracting apacket identifier number from a header in a packet and checking thepacket identifier number with the packet identifier table.
 15. The inputprocessing device of claim 11, wherein the input packet data includes aplurality of packets, and wherein the timestamp value generated by thetime reference generator corresponds to a time period during which apacket passes through the re-multiplexing module.